In flash memory and EEPROM (Electrically Erasable Programmable Read Only Memory) devices, a floating gate transistor and a control gate are critical components for performing read and write operations.
Prior art processes for forming a memory cell including control gate and floating gate components typically require a complex series of photolithographic patterning and etching processes to form the floating gate, and overlying inter-gate dielectric, and control gate. For example, in prior art processes, a complex series of steps has been required to form floating gate electrodes, followed by formation of an inter-gate dielectric layer, followed by formation of an overlying polysilicon layer with a hardmask and a complex multi-step etching process to form adjacent self-aligned electrodes (e.g., word line electrodes).
The formation of logic (CMOS) devices and PNVM devices according to prior art processes is generally incompatible as the PNVM device process flow requires several extra dielectric layer formation, patterning, and etching steps to form the PNVM device cell components. When the formation of logic (CMOS) devices and PNVM devices takes place in parallel on separate active area portions of a semiconductor process wafer, the process flow becomes even more complex in adding the required processing steps to form the PNVM cell areas. As a result, the production cycle time is lengthy and the production cost is high.
There is therefore a need in the PNVM device processing art to develop novel PNVM devices that are compatible with logic device processes to improve a process flow while maintaining device operability and reliability.
It is therefore an object of the invention to provide a novel PNVM device that is compatible with logic device processes to improve a process flow while maintaining device operability and reliability, in addition to overcoming other deficiencies and shortcomings of the prior art.